1. Field of the Invention
The present invention generally relates to decoupling capacitors and more particularly to testing such capacitors having high dielectric material between the metal wirings of the capacitor.
2. Description of the Related Art
Conventional microprocessor clock rates are approaching the gigahertz range of operation and thereby create noise problems. As a result, large decoupling capacitors are used between a power supply and ground to provide enough noise immunity for proper circuit operation. Options include the integration of large plate capacitors, which would essentially occupy the entire chip above the active silicon surface, and trench capacitors embedded in the silicon substrate. However, large plate capacitors add significant critical area and thereby create a difficult yield problem. On the other hand, trench capacitors require extra silicon area which increases the chip size. Both solutions add significant process complexity and cost.
In view of the foregoing and other problems of the conventional methods, it is, therefore, an object of the present invention to provide a decoupling capacitor for a semiconductor device. The decoupling capacitor may include a first low dielectric insulator layer such as fluorinated glass. The capacitor may also include a low resistance conductor formed into at least two interdigitized patterns on the surface of the low dielectric insulator layer such as fluorinated glass. Each of the two patterns may be adjacent to the other such that their sidewalls form plates of the capacitor. The capacitor may also include a high dielectric constant material provided between the two interdigitized patterns.
The high dielectric constant material may comprise tantalum pentoxide or silicon nitride. The capacitor may also include a second low dielectric insulator layer provided on the high dielectric constant material and the patterns. Even further, the capacitor may include a polish stop material provided on each of the two patterns. The polish stop, which may be non-conformally deposited on the interdigitized patterns, may include diamond-like carbon or silicon nitride.
Another object of the present invention is to provide a circuit for monitoring a plurality of capacitors. The circuit may include a charge monitoring circuit coupled to each capacitor segment and a coupling circuit for selectively coupling and decoupling one of the capacitor segments from among a plurality of states. A control circuit may also be provided for sequentially controlling the coupling circuit of each of the capacitor segments so as to disconnect a failed capacitor segment while the other capacitor segments are monitored.
The control circuit may include at least one n-channel transistor connected between the control circuit and one plate of the capacitor segment. The control circuit may further include a fuse circuit provided between the capacitor segment and the at least one n-channel transistor.
The coupling circuit may include at least one p-channel transistor connected between the control circuit and one plate of the capacitor segment. The other plate of the capacitor segment may be connected to a ground potential.
The coupling circuit may further include a fuse circuit connected between the control circuit and the p-channel transistor. A charge monitoring circuit may output a signal based on the amount of current flowing through the capacitor segment when the coupling segment is in a test state. The charge monitoring circuit may include an integrator circuit.
Other objects, advantages and salient features of the invention will become apparent from the following detailed description taken in conjunction with the annexed drawings, which disclose preferred embodiments of the invention.